The present invention relates to integrated circuit structures and fabrication methods, and particularly to storage cells.
Loadless SRAMs have been an important recent development in memory technology. Like conventional 4T or 6T SRAMs, loadless SRAMs include a xe2x80x9clatchxe2x80x9d (a cross-coupled pair of driver transistors) whose state corresponds to the stored data; but conventional SRAMs must have a load of some sort to maintain the state of the latch. (In a conventional 4T SRAM cell the load is provided by a special high-impedance element, which complicates fabrication; in a conventional 6T SRAM cell the load is provided by another pair of cross-coupled transistors, of opposite type to the driver transistors.) Loadless SRAMs do not have any such load: instead, the data state is maintained merely by leakage current through the pass transistors.
To maintain the data state, the leakage current into the high node must be greater than the leakage current through the driver transistor which connects the high node to ground.
The present application discloses an improvement to storage cells. The wordline to accessed cells during read is pulled down incrementally, or in a gradual fashion, to allow the accessed storage cell to reach a more stable state before the pass transistors are fully turned on, which allows the cell to not be upset when accessed. It also allows the cells to be maintained at lower power consumption when not accessed or during standby.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
saves power in standby;
higher power only used in accessed rows, leaving unaddressed cells to sag and save power.